Method and circuit for reducing current surge

ABSTRACT

Systems and methods are provided for reducing surge current in power gated designs. In one aspect, a storage capacitor supplies a portion of the current used to power up a circuit. The storage capacitor may be charged from a power supply or other source. When the circuit is to be powered up, the circuit is connected to the power supply and the storage capacitor. As a result, current is supplied to the circuit from the power supply and the storage capacitor to power up the circuit. Because a portion of the current used to power up the circuit is supplied from the storage capacitor, the amount of current needed from the power supply to power up the circuit can be reduced, thereby reducing current surge through the power supply. The storage capacitor may be shared by multiple circuits.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Divisional Application of the U.S. patentapplication Ser. No. 13/645,427, filed Oct. 4, 2012, which isincorporated herein by reference in its entirety.

The present description relates generally to power gating, and moreparticularly, to power gating with reduced current surge.

BACKGROUND

Power gating may be used to reduce power leakage by a circuit in anelectronic system, in which a power controller uses a switch toselectively connect the circuit to a power supply depending on whetherthe circuit is in operation. When the circuit is in operation, the powercontroller turns on the switch to connect the circuit to the powersupply through the switch. When the circuit is turned off or in standbymode, the power controller turns off the switch to disconnect thecircuit from the power supply. The circuit may comprise a memory, logicor another type of circuit. The switch may have a low resistance so thatpower dissipation across the switch is minimized when the circuit isconnected to the power supply through the switch.

Power gating may cause a large current surge through the power supplywhen the switch is first turned on due to the low resistance of theswitch and a large voltage difference between the power supply and thecircuit when the switch is first turned on. The current surge may createa large IR voltage drop in the power supply because of power gridresistance and/or package inductance. This drop may cause other circuitsconnected to the power supply to lose their state, thus causingfunctionality failure.

BRIEF DESCRIPTION OF THE DRAWINGS

Certain features of the subject technology are set forth in the appendedclaims. However, for purpose of explanation, several embodiments of thesubject technology are set forth in the following figures.

FIG. 1 illustrates an example of a variable-resistance switch forselectively connecting a circuit to a power supply.

FIG. 2 illustrates an example implementation of the variable-resistanceswitch.

FIG. 3 illustrates an example power system including a storage capacitoraccording to aspects of the subject technology.

FIG. 4 illustrates an example power system including a storage capacitorthat is shared by circuits according to aspects of the subjecttechnology.

FIG. 5 illustrates an example power system including a storage capacitorthat is shared by memory banks according to aspects of the subjecttechnology.

FIG. 6 illustrates an example power system including a storage capacitorthat is shared by memory banks and logic according to aspects of thesubject technology.

FIG. 7 illustrates an example power system in which circuits are poweredby different power supplies according to aspects of the subjecttechnology.

FIG. 8 illustrates an example power system in which a storage capacitoris charged by a separate power supply according to aspects of thesubject technology.

FIG. 9 illustrates another example power system according to aspects ofthe subject technology.

FIG. 10 is a flowchart illustrating an example method for managing poweraccording to aspects of the subject technology.

DETAILED DESCRIPTION

The detailed description set forth below is intended as a description ofvarious configurations of the subject technology and is not intended torepresent the only configurations in which the subject technology may bepracticed. The appended drawings are incorporated herein and constitutea part of the detailed description. The detailed description includesspecific details for the purpose of providing a thorough understandingof the subject technology. However, the subject technology is notlimited to the specific details set forth herein and may be practicedwithout one or more of the specific details. In some instances,structures and components are shown in block diagram form in order toavoid obscuring the concepts of the subject technology.

FIG. 1 illustrates an approach for preventing a large current surge inpower-gated designs, in which a switch S1 with a variable resistance isused to selectively connect a circuit 110 to a power supply having avoltage of Vdd. A power controller 120 controls switching of switch S1to manage power to the circuit 110. The power controller 120 alsoadjusts the resistance of switch S1 between a low resistance and a highresistance to prevent a large current surge.

When the power controller 120 first turns on switch S1 (e.g., to wake upthe circuit 110), the power controller 120 sets switch S1 to the highresistance to limit the current flow to the circuit 110 through switchS1, thereby preventing a large current surge through the power supply.When the voltage of the circuit 110 reaches a certain level, the powercontroller 120 sets switch S1 to the low resistance to finish poweringup the circuit 110 to the power supply voltage Vdd and minimize powerdissipation across switch S1.

To provide variable resistance, switch S1 may be implemented using twoor more switches with different resistances, an example of which isshown in FIG. 2. In this example, switch S1 includes a low-resistanceswitch S1 _(L) and a high-resistance switch S1 _(H). The high-resistanceswitch S1 _(H) may have a resistance that is one or more orders ofmagnitude higher than the resistance of the low-resistance switch S1_(L). Each switch may be implemented using a p-channel field-effecttransistor (as shown in FIG. 2), in which the switches may be givendifferent resistances by fabricating the corresponding transistors withdifferent gate widths. In this example, the transistor implementing thelow-resistance switch S1 _(L) has a wider gate (and hence lowerresistance) than the transistor implementing the high-resistance switchS1 _(H).

For the implementation in FIG. 2, when the power controller 120 firstturns on switch S1, the power controller 120 may set the resistance ofswitch S1 to the high resistance by turning on the high-resistanceswitch S1 _(H) with the low-resistance switch S1 _(L) turned off. Whenthe voltage of the circuit 110 reaches a certain level, the powercontroller 120 may reduce the resistance of the switch S1 to the lowresistance by turning on the low-resistance switch S1 _(L). When thelow-resistance switch S1 _(L) is turned on, the high-resistance switchS1 _(H) may be left on or turned off.

Thus, the power controller 120 prevents a large current surge throughthe power supply by initially setting switch S1 to the high resistance.The high resistance limits the amount of current drawn from the powersupply to the circuit 110 through switch S1, thereby preventing a largecurrent surge. However, limiting the current flow to the circuit 110 maycause a delay in powering up the circuit 110 to Vdd. For example, whenthe circuit includes a memory, the delay may increase the wait time foraccessing the memory, causing a bottleneck in performance.

FIG. 3 shows an example power system 310 according to some aspects ofthe subject technology. The power system 310 includes switches S2 andS3, a storage capacitor C_(S), and a power controller 320. The powersystem 310 can be used to reduce the latency associated with theapproach in FIG. 1 by using the storage capacitor C_(S) to provideadditional current for powering up the circuit 110.

When the circuit 110 is turned off or in standby mode, the powercontroller 320 charges up the storage capacitor C_(S) to Vdd by turningon switch S2 while leaving switch S3 turned off. This allows current toflow from the power supply to the storage capacitor C_(S) to charge thestorage capacitor C_(S) to Vdd while keeping the storage capacitor C_(S)isolated from the circuit 110. The power controller 320 may also chargeup the storage capacitor C_(S) when the circuit 110 is in normaloperation, assuming that the amount of current drawn from the powersupply to charge the storage capacitor C_(S) is not enough to disruptthe normal operation of the circuit 110.

When the circuit 110 is to be powered up to Vdd (e.g., woken up), thepower controller 320 may turn off switch S2 to disconnect the storagecapacitor C_(S) from the power supply and turn on switch S3 to connectthe storage capacitor C_(S) to the circuit 110 through switch S3. As aresult, the storage capacitor C_(S) discharges to the circuit 110through switch S3, thereby supplying current to the circuit 110.

The power controller 320 may also turn on switch S1 in thehigh-resistance state to supply current to the circuit 110 from thepower supply. Thus, current may be supplied to the circuit 110 from boththe power supply through switch S1 and the storage capacitor C_(S)through switch S3.

When the voltage of the circuit 110 reaches a certain level, the powercontroller 320 may reduce the resistance of switch S1 to the lowresistance to finish powering up the circuit 110 to Vdd. At about thistime, the power controller 320 may turn off switch S3 to disconnect thecircuit 110 from the storage capacitor C_(S).

After the circuit 110 is powered up to Vdd, the circuit 110 may beginnormal operation. For the example where the circuit 110 includes amemory, the memory may be capable of performing read/write operationswhen the memory voltage is approximately Vdd. During normal operation ofthe circuit 110, the power controller 320 leaves switch S1 turned on inthe low-resistance state to supply power to the circuit 110 from thepower supply.

Thus, the storage capacitor C_(S) supplies additional current for wakingup the circuit 110. The additional current can be used to reduce thewakeup time for the circuit 110 without increasing the current surgethrough the power supply. This is because the additional current fromthe storage capacitor C_(S) increases the total amount of currentavailable to power up the circuit 110 without having to draw morecurrent from the power supply through switch S1. Therefore, for a givencurrent surge through the power supply, the storage capacitor C_(S) cansignificantly reduce the wakeup time for the circuit 110 compared withthe approach in FIG. 1.

The additional current from the storage capacitor C_(S) can also be usedto reduce the current surge through the power supply without increasingthe wakeup time. This is because, when the current flow through switchS1 is reduced to reduce the current surge, the additional current fromthe storage capacitor C_(S) can be used to make up the difference toachieve the same wakeup time.

The additional current from the storage capacitor C_(S) can also be usedto achieve both a reduction in wakeup time and a reduction in currentsurge. For example, the current flow through switch S1 may be reduced toreduce the current surge through the power supply (e.g., by increasingthe resistance of switch S1). At the same time, the storage capacitorC_(S) may have a capacitance with enough charge-storage capacity tosupply a current that is larger than the current reduction throughswitch S1, thereby achieving reductions in both wakeup time and currentsurge.

In some aspects, during normal operation of the circuit 110, the powercontroller 320 may turn on switch S2 with switch S3 turned off to chargeup the storage capacitor C_(S) to Vdd. The charge-up time for thestorage capacitor C_(S) may be relatively slow compared with the time topower up the circuit 110. This is because the storage capacitor C_(S)may not be needed to supply current to the circuit 110 until the nextwakeup cycle. Thus, switch S2 may have a relatively high resistance(compared with the low resistance of switch S1) when turned on so thatonly a small amount of current is drawn from the power supply to chargeup the storage capacitor C_(S). Switch S3, on the other hand, may have arelatively low resistance (e.g., comparable to the low resistance ofswitch S1) when turned on to allow large current flow from the storagecapacitor C_(S) to the circuit 110 to quickly power up the circuit 110.

The power controller 320 may leave switch S2 turned on until the nextwakeup cycle. Leaving switch S2 turned on allows the power supply tomaintain the charge of the storage capacitor C_(S) at Vdd when thestorage capacitor C_(S) is leaky.

When the circuit 110 is to be turned off or placed in standby mode, thepower controller 320 may turn off switch S1 to disconnect the circuit110 from the power supply. In standby, the voltage of the circuit 110may be reduced to a voltage level below the power supply Vdd to reducepower leakage. The lower voltage in standby may be provided by a circuit(not shown) that converts the power supply voltage Vdd to the lowervoltage or may be provided by a separate power supply (not shown).

As discussed above, the power controller 320 may turn on switch S2during normal operation of the circuit 110 to charge up the storagecapacitor C_(S). Alternatively, the power controller 320 may turn offswitch S2 during normal operation of the circuit 110 and wait until thecircuit is turned off or in standby mode to turn on switch S2 to chargeup the storage capacitor C_(S).

As discussed above, during power up, the power controller 320 may adjustthe resistance of switch S1 from the high resistance to the lowresistance when the voltage of the circuit 110 reaches a certain voltagelevel. This voltage level may be determined based on a voltage level atwhich the current flow through switch S1 at the low resistance is withina current limit. The current limit may be defined by a specification forthe power supply (e.g., based on the maximum IR drop that can betolerated in the power supply without causing functionality failure inother circuits connected to the power supply). The current flow throughswitch S1 at the low resistance may be given approximately by:

$\begin{matrix}{I = \frac{{Vdd} - {Vc}}{R}} & (1)\end{matrix}$

where I is the current through switch S1, R is the low resistance, andVc is the voltage of the circuit 110. As shown in Eq. (1), the current Ithrough switch S1 at the low resistance decreases as the voltage of thecircuit 110 approaches the power supply voltage Vdd. Thus, given acurrent limit for the current I through switch S1, a voltage level maybe determined at which the resistance of switch S1 can be reduced whilestaying within the current limit.

In some aspects, a time delay may be determined between the time thatswitch S1 is first turned on in the high-resistance state and the timethat the resistance of switch S1 is reduced from the high resistance tothe low resistance. The time delay may be based on the time it takes thevoltage Vc of the circuit 110 to reach a voltage level at which thecurrent I through switch S1 at the low resistance is within the currentlimit. This time may be determined by performing circuit simulations,testing and/or calculations. Once determined, the power controller 320may be programmed with the time delay.

In this example, when the circuit 110 is to be woken up, the powercontroller 320 may first turn on switch S1 in the high-resistance stateto supply current to the circuit 110 from the power supply, and turn onswitch S3 to supply additional current to the circuit 110 from thestorage capacitor C_(S). After the programmed time delay, the powercontroller 320 may reduce the resistance of switch S1 from the highresistance to the low resistance to finish powering up the circuit toVdd. At about this time, the power controller 320 may turn off switch S3to allow the storage capacitor C_(S) to be charged up for the nextwakeup cycle.

Alternately, the power controller 320 includes a voltage sensorconfigured to sense the voltage Vc of the circuit 110. When the sensedvoltage reaches a certain voltage, the power controller 320 may reducethe resistance of switch S1 from the high resistance to the lowresistance to finish powering up the circuit 110 to Vdd.

FIG. 4 shows an example power system 410 according to some aspects ofthe subject technology. The power system 410 is capable of managingpower for two circuits 110 a and 110 b sharing a power supply. Thecircuits 110 a and 110 b may be integrated on the same chip or may be onseparate chips.

The power system 410 includes switches S1 a and S1 b for selectivelyconnecting the circuits 110 a and 110 b, respectively, to the powersupply. Each of these switches may be a variable-resistance switch, asshown in FIG. 4. The power system 410 also includes a power controller420, and a storage capacitor C_(S) that is shared between the circuits110 a and 110 b, as discussed further below. The power system 410further includes switch S2 for selectively connecting the storagecapacitor C_(S) to the power supply, and switches S3 a and S3 b forselectively connecting the circuits 110 a and 110 b, respectively, tothe storage capacitor C_(S).

The power controller 420 may independently control switches S1 a and S1b, allowing the power system 410 to independently control power to thecircuits 110 a and 110 b. For example, if both circuits 110 a and 110 bare in normal operation, then the power controller 420 may turn on bothswitches S1 a and S1 b so that both circuits 110 a and 110 b areconnected to the power supply. If one of the circuits 110 a and 110 b isin normal operation while the other circuit is turned off or in standby,then the power controller 420 may turn on the switch for the circuitthat is in operation, and turn off the switch for the circuit that isturned off or in standby. If both circuits 110 a and 110 b are turnedoff or in standby mode, then the power controller 420 may turn off bothswitches S1 a and S1 b, in which case both circuits 110 a and 110 b aredisconnected from the power supply.

The power controller 420 may charge up the storage capacitor C_(S) tothe power supply Vdd by turning on switch S2. The power controller 420may do this when both circuits 110 a and 110 b are in normal operation,when one of the circuits 110 a and 110 b is in normal operation and theother circuit is turned off or in standby, and/or when both circuits 110a and 110 b are turned off or in standby.

When circuit 110 a is to be woken up, the power controller 420 may turnoff switch S2, and turn on switch S3 a while leaving switch S3 b turnedoff. This creates a current path from the storage capacitor C_(S) tocircuit 110 a, allowing the storage capacitor C_(S) to supply current tocircuit 110 a through switch S3 a. The power controller 420 may alsoturn on switch S1 a in the high-resistance state to supply current tocircuit 110 a from the power supply. When the voltage of circuit 110 areaches a certain voltage level, the power controller 420 may reduce theresistance of switch S1 a to the low resistance to finish powering upcircuit 110 a to Vdd. At about this time, the power controller 420 mayturn off switch S3 a to allow the storage capacitor C_(S) to be chargedup for the next wakeup cycle.

When circuit 110 b is to be woken up, the power controller 420 may turnoff switch S2, and turn on switch S3 b while leaving switch S3 a turnedoff. This creates a current path from the storage capacitor C_(S) tocircuit 110 b, allowing the storage capacitor C_(S) to supply current tocircuit 110 b through switch S3 b. The power controller 420 may alsoturn on switch S1 b in the high-resistance state to supply current tocircuit 110 b from the power supply. When the voltage of circuit 110 breaches a certain voltage level, the power controller 420 may reduce theresistance of switch S1 b to the low resistance to finish powering upcircuit 110 b to Vdd. At about this time, the power controller 420 mayturn off switch S3 b to allow the storage capacitor C_(S) to be chargedup for the next wakeup cycle.

Thus, the power controller 420 may independently control switches S3 aand S3 b to direct current from the storage capacitor C_(S) to thecircuit being woken up. This allows each circuit 110 a and 110 b to usethe storage capacitor C_(S) when needed to wake up. Because circuits 110a and 110 b share the storage capacitor C_(S), two separate storagecapacitors are not needed to wake up circuits 110 a and 110 b, therebyreducing the chip area needed for the power system 310.

FIG. 5 shows an example in which the circuit includes a first memorybank 510 a and a second memory bank 510 b. Each memory bank 510 a and510 b may include static random access memory (SRAM) or other type ofmemory. The memory banks 510 a and 510 b may be integrated on the samechip. In addition, the memory banks 510 a and 510 b may be integrated onthe same chip as other circuitry (e.g., one or more processors) toprovide embedded memory. For example, the memory banks 510 a and 510 bmay be integrated on the same chip as a processor to provide theprocessor with cache memory.

Each memory bank 510 a and 510 b may support read/write operations whenthe voltage of the memory bank is Vdd. Thus, the data in each memorybank 510 a and 510 may be accessible (e.g., by a processor) when thevoltage of the memory bank is Vdd.

When a memory bank 510 a and 510 b is not being accessed, the voltage ofthe memory bank may be reduced from Vdd to a “retention voltage” toconserve power. The retention voltage may be sufficient to retain thedata in the memory bank, but insufficient to access the data in thememory bank (i.e., too low for read/write operations). For example, theretention voltage may be approximately 600 mV while Vdd may beapproximately 900 mV. Reducing the voltage of the memory bank to theretention voltage when the memory bank is not being accessed reduces theleakage power of the memory bank, thereby conserving power. Theretention voltage may be provided by a circuit (not shown) that convertsthe power supply voltage Vdd to the retention voltage or may be providedby a separate power supply (not shown).

In this example, the power controller 420 may independently manage powerto the memory banks 510 a and 510 b. The power controller 410 maydynamically connect the first memory bank 510 a to the power supplyusing switch S1 a depending on whether the first memory bank 510 a iscurrently being accessed. When the first memory bank 510 a is beingaccessed (e.g., by a processor), the power controller 420 may turn onswitch S1 a, and, when the first memory bank 510 a is not beingaccessed, the power controller 420 may turn off switch S1 a.

The power controller 420 may dynamically connect the second memory bank510 b to the power supply using switch S1 b depending on whether thesecond memory bank 510 b is currently being accessed. When the secondmemory bank 510 b is being accessed, the power controller 420 may turnon switch S1 b, and, when the second memory bank 510 b is not beingaccessed, the power controller 420 may turn off switch S1 b.

When the first memory bank 510 a is to be accessed, the power controller420 may raise the voltage of the first memory bank 510 a from theretention voltage to Vdd by supplying current from the storage capacitorC_(S) to the first memory bank. The power controller 420 may do this byturning off switch S2 to disconnect the storage capacitor C_(S) from thepower supply, and turning on switch S3 a with switch S3 b turned off todirect current flow from the storage capacitor C_(S) to the first memorybank 510 a. The power controller 420 may also turn on switch S1 a in thehigh-resistance state to supply current to the first memory bank 510 afrom the power supply. When the voltage of the first memory bank 510 areaches a certain voltage level, the power controller 420 may reduce theresistance of switch S1 a to finish powering up the first memory bank510 a to Vdd. At about this time, the power controller 420 may turn offswitch S3 a to allow the storage capacitor C_(S) to be charged up forthe next wakeup cycle. When the first memory bank 510 a is no longerbeing accessed, the power controller may turn off switch S1 a to reducepower leakage.

When the second memory bank 510 b is to be accessed, the powercontroller 420 may raise the voltage of the second memory bank 510 bfrom the retention voltage to Vdd by supplying current from the storagecapacitor C_(S) to the second memory bank. The power controller 420 maydo this by turning off switch S2 to disconnect the storage capacitorC_(S) from the power supply, and turning on switch S3 b with switch S3 aturned off to direct current flow from the storage capacitor C_(S) tothe second memory bank 510 b. The power controller 420 may also turn onswitch S1 b in the high-resistance state to supply current to the secondmemory bank 510 b from the power supply. When the voltage of the secondmemory bank 510 b reaches a certain voltage level, the power controller420 may reduce the resistance of switch S1 b to finish powering up thesecond memory bank 510 b to Vdd. At about this time, the powercontroller 420 may turn off switch S3 b to allow the storage capacitorC_(S) to be charged up for the next wakeup cycle. When the second memorybank 510 b is no longer being accessed, the power controller may turnoff switch S1 b to reduce power leakage.

In this example, access to the memory banks 510 a and 510 b may becontrolled by a memory controller (not shown). When a processor needsaccess to a memory address corresponding to a particular memory bank,the memory controller may instruct the power controller 420 to wake upthe memory bank. When the processor is finished accessing the memorybank, the memory controller may instruct the power controller 420 toplace the memory bank back in standby, wherein the voltage of the memorybank is held at the retention voltage.

The capacitance of the storage capacitor C_(S) may be chosen based onthe capacitance of a memory bank, in which the capacitance of the memorybank may be approximated by a total capacitance from all of the memorycells in the memory bank. When the storage capacitor C_(S) discharges tothe memory bank, the storage capacitor is capable of raising the voltageof the memory bank to approximately:

$\begin{matrix}{V = \frac{{{Vr} \cdot {Cm}} + {{Vdd} \cdot {Cs}}}{{Cm} + {Cs}}} & (2)\end{matrix}$

where Vr is the retention voltage of the memory bank, Cm is the totalcapacitance of the memory bank, and Cs is the capacitance of the storagecapacitor. Thus, for a given memory capacitance Cm and retention voltageVr, Eq. (2) may be used to determine the capacitance of the storagecapacitor C_(S) needed to raise the voltage of the memory bank to adesired voltage level (e.g., voltage level at which the resistance ofthe switch S1 a or S1 b is to be reduced).

The memory banks 510 a and 510 b may share the storage capacitor C_(S)with other circuitry. For example, the memory banks 510 a and 510 b maybe integrated with other circuitry on the same chip to provide embeddedmemory.

FIG. 6 illustrates an example power system 610 in which the storagecapacitor C_(S) is shared by the memory banks 510 a and 510 b and logiccircuit 615, all of which may be integrated on the same chip. Logiccircuit 615 may include a processor that uses the memory banks 510 a and510 b for cache memory or other logic circuitry. In this example, thepower system 610 further includes switch S1 c to selectively connectlogic circuit 615 to the power supply and switch S3 c to selectivelyconnect logic circuit 615 to the storage capacitor C_(S). Switch S1 cmay be a variable-resistance switch. For ease of illustration, theconnections between the power controller and the gates of the switchesare not shown in FIG. 6.

When logic circuit 615 is turned off or in standby, the power controller(not shown in FIG. 6) may turn off switch S1 c to disconnect logiccircuit 615 from the power supply. When logic circuit 615 is to be wokenup, the power controller may turn off switch S2 to disconnect thestorage capacitor C_(S) from the power supply, and turn on switch S3 cwith switches S3 a and S3 b turned off to direct current flow from thestorage capacitor C_(S) to logic circuit 615. The power controller mayalso turn on switch S1 c in the high-resistance state to supply currentto the logic circuit 615 from the power supply. When the voltage oflogic circuit 615 reaches a certain voltage level, the power controllermay reduce the resistance of switch S1 c to finish powering up logiccircuit 615 to Vdd. At about this time, the power controller may turnoff switch S3 c to allow the storage capacitor C_(S) to be charged upfor the next wakeup cycle. When logic circuit 615 is to be turned off orplaced in standby, the power controller may turn off switch S1 c.

In this example, the power controller may wake up the memory banks 510 aand 510 b in a similar manner as in the power system 410 shown in FIG.5. To supply current from the storage capacitor C_(S) to the firstmemory bank 510 a, the power controller may turn on switch S3 a whileleaving switches S3 b and S3 c turned off. To supply current from thestorage capacitor C_(S) to the second memory bank 510 b, the powercontroller may turn on switch S3 b while leaving switches S3 a and S3 cturned off.

The storage capacitor C_(S) is not limited to being shared by threecircuits, and may be shared by a larger number of circuits. For eachcircuit sharing the storage capacitor C_(S), the power system mayinclude a separate power switch for selectively connecting the circuitto the power supply and a separate capacitor switch for selectivelyconnecting the circuit to the storage capacitor C_(S). When a particularcircuit is to be woken up, the power controller may turn on therespective capacitor switch while leaving the capacitor switches for theother circuits turned off. This creates a current path between thestorage capacitor C_(S) and the circuit being woken up. The powercontroller may also turn on the respective power switch in thehigh-resistance state to supply current to the circuit from the powersupply. When the voltage of the circuit reaches a certain voltage level,the power controller may reduce the resistance of the respective powerswitch to finish powering up the circuit to Vdd. When the circuit is tobe turnoff or placed in standby, the power controller may turn off therespective power switch.

The switch used to selectively connect the storage capacitor C_(S) tothe power supply may be turned on when none of the circuits arecurrently being woken up to charge up the storage capacitor C_(S) toVdd. When this switch is turned on, all of the capacitor switches may beturned off to isolate the storage capacitor C_(S) from the circuitsduring charge up.

FIG. 7 illustrates an example power system 710 in which circuits 110 aand 110 b are selectively connected to different power supplies byswitches S1 a and S1 b, respectively. Circuit 110 a is selectivelyconnected to a first power supply having a voltage of Vdd1, and circuit110 b is selectively connected to a second power supply having a voltageof Vdd2. Thus, circuits 110 a and 110 b may receive power at differentpower supply voltages (Vdd1 and Vdd2, respectively). The storagecapacitor C_(S) may be selectively connected to the first power supplyby switch S2 to charge the storage capacitor C_(S), as shown in theexample in FIG. 7. Alternatively, the storage capacitor C_(S) may beselectively connected to the second power supply by switch S2 to chargethe storage capacitor C_(S) (not shown).

FIG. 8 illustrates an example power system 810 in which circuits 110 aand 110 b are selectively connected to a power supply having a voltageof Vdd by switches S1 a and S1 b, respectively. In this example, thestorage capacitor C_(S) is selectively connected to the separate powersupply having a voltage of Vddc by switch S2. The voltage Vddc may behigher than power supply voltage Vdd so that the storage capacitor C_(S)can be charged to a higher voltage. Switches S3 a and S3 b may be turnedoff when the storage capacitor C_(S) is charging to isolate the storagecapacitor from circuits 110 a and 110 b. Making Vddc higher than Vddenables the storage capacitor C_(S) to supply more current to circuit110 a or 110 b and/or raise the voltage of circuit 110 a or 110 b to ahigher voltage. In this example, when the storage capacitor C_(S) isused to supply current to a memory, the storage capacitor C_(S) iscapable of raising the voltage of the memory to:

$\begin{matrix}{V = \frac{{{Vr} \cdot {Cm}} + {{Vddc} \cdot {Cs}}}{{Cm} + {Cs}}} & (3)\end{matrix}$

FIG. 9 illustrates an example power system 910 in which circuits 110 aand 110 b are selectively connected to different power supplies byswitches S1 a and S1 b, respectively. Circuit 110 a is selectivelyconnected to a first power supply having a voltage of Vdd1, and circuit110 b is selectively connected to a second power supply having a voltageof Vdd2. Thus, circuits 110 a and 110 b may receive power at differentpower supply voltages (Vdd1 and Vdd2, respectively). The storagecapacitor is selectively connected to a separate power supply having avoltage of Vddc by switch S2.

FIGS. 1-9 show examples in which each switch is implemented using ap-channel field effect transistor (PFET). A PFET switch may be turnedoff by applying a voltage of Vdd to the gate of the PFET switch, and maybe turned on by lowering the voltage at the gate (e.g., to ground). Itis to be appreciated that the subject technology is not limited to PFETswitches, and that any suitable type of electronic switch may be used.

FIG. 10 is a flowchart illustrating a method 1000 for power managementaccording to some aspects of the subject technology. The method may beperformed by the power controller 320 or 420.

A storage capacitor is charged (1010). A circuit to be powered up (e.g.,from standby) is connected to a power supply to supply current to thecircuit from the power supply (1020). The circuit is connected to thestorage capacitor to supply additional current to the circuit from thestorage capacitor (1030). As discussed above, the additional currentsupplied from the storage capacitor can be used to achieve a reductionin current surge through the power supply. The circuit may be connectedto the power supply and the storage capacitor concurrently to supplycurrent to the circuit simultaneously from the power supply and thestorage capacitor.

For the example in which the storage capacitor is charged by connectingthe storage capacitor to the power supply, the storage capacitor may bedisconnected from the power supply at any time after the storagecapacitor is charged (e.g., to the power supply voltage). In thisexample, the storage capacitor may be disconnected from the power supplyjust before the storage capacitor is connected to the circuit (1030).

When the circuit is connected to the power supply (1020), the circuitmay be initially connected to the power supply through avariable-resistance switch in a high-resistance state to limit thecurrent flow from the power supply. When the voltage of the circuitreaches a certain voltage level, the resistance of the switch may bereduced.

It is to be appreciated that the circuit may be connected to the storagecapacitor (1030) before the circuit is connected to the power supply(1020).

In the disclosure, the storage capacitor C_(S) may be connected to a“charge source” by switch S2 to charge the storage capacitor C_(S). Thecharge source may be the power supply used to power circuit 110 a, aseparate power supply, or other source capable of charging the storagecapacitor C_(S). Thus, the subject technology is not limited to aparticular type of charge source for charging the storage capacitorC_(S).

The functions described above can be implemented in digital electroniccircuitry, in computer software, firmware or hardware. The techniquescan be implemented using one or more computer program products.Programmable processors and computers can be included in or packaged asmobile devices. The processes and logic flows can be performed by one ormore programmable processors and by one or more programmable logiccircuitry.

Some implementations can include electronic components, such asmicroprocessors, storage and memory that store computer programinstructions in a machine-readable or computer-readable medium(alternatively referred to as computer-readable storage media,machine-readable media, or machine-readable storage media). Someexamples of such computer-readable media include RAM, ROM, read-onlycompact discs (CD-ROM), recordable compact discs (CD-R), rewritablecompact discs (CD-RW), read-only digital versatile discs (e.g., DVD-ROM,dual-layer DVD-ROM), a variety of recordable/rewritable DVDs (e.g.,DVD-RAM, DVD-RW, DVD+RW, etc.), flash memory (e.g., SD cards, mini-SDcards, micro-SD cards, etc.), magnetic and/or solid state hard drives,ultra density optical discs, any other optical or magnetic media, andfloppy disks. The computer-readable media can store a computer programthat is executable by at least one processing unit and includes sets ofinstructions for performing various operations. Examples of computerprograms or computer code include machine code, such as is produced by acompiler, and files including higher-level code that are executed by acomputer, an electronic component, or a microprocessor using aninterpreter.

Some implementations can be performed by a microprocessor or multi-coreprocessors that execute software. Some implementations can be performedby one or more integrated circuits, such as application specificintegrated circuits (ASICs) or field programmable gate arrays (FPGAs).In some implementations, such integrated circuits can executeinstructions that are stored on the circuit itself.

Many of the above-described features and applications may be implementedas software processes that are specified as a set of instructionsrecorded on a computer readable storage medium (also referred to ascomputer readable medium). When these instructions are executed by oneor more processing unit(s) (e.g., one or more processors, cores ofprocessors, or other processing units), they cause the processingunit(s) to perform the actions indicated in the instructions. Examplesof computer readable media include, but are not limited to, CD-ROMs,flash drives, RAM chips, hard drives, EPROMs, etc. The computer readablemedia does not include carrier waves and electronic signals passingwirelessly or over wired connections.

In this specification, the term “software” is meant to include firmwareresiding in read-only memory or applications stored in magnetic storage,which can be read into memory for processing by a processor. Also, insome implementations, multiple software aspects of the subjectdisclosure can be implemented as sub-parts of a larger program whileremaining distinct software aspects of the subject disclosure. In someimplementations, multiple software aspects can also be implemented asseparate programs. Finally, any combination of separate programs thattogether implement a software aspect described here is within the scopeof the subject disclosure. In some implementations, the softwareprograms, when installed to operate on one or more electronic systems,define one or more specific machine implementations that execute andperform the operations of the software programs.

A computer program (also known as a program, software, softwareapplication, script, or code) can be written in any form of programminglanguage, including compiled or interpreted languages, declarative orprocedural languages, and it can be deployed in any form, including as astand alone program or as a module, component, subroutine, object, orother unit suitable for use in a computing environment. A computerprogram may, but need not, correspond to a file in a file system. Aprogram can be stored in a portion of a file that holds other programsor data (e.g., one or more scripts stored in a markup languagedocument), in a single file dedicated to the program in question, or inmultiple coordinated files (e.g., files that store one or more modules,sub programs, or portions of code). A computer program can be deployedto be executed on one computer or on multiple computers that are locatedat one site or distributed across multiple sites and interconnected by acommunication network.

The previous description is provided to enable any person skilled in theart to practice the various aspects described herein. Variousmodifications to these aspects will be readily apparent to those skilledin the art, and the generic principles defined herein may be applied toother aspects. Thus, the claims are not intended to be limited to theaspects shown herein, but are to be accorded the full scope consistentwith the language claims, wherein reference to an element in thesingular is not intended to mean “one and only one” unless specificallyso stated, but rather “one or more.” Unless specifically statedotherwise, the term “some” refers to one or more. Pronouns in themasculine (e.g., his) include the feminine and neuter gender (e.g., herand its) and vice versa. Headings and subheadings, if any, are used forconvenience only and do not limit the subject disclosure.

The predicate words “configured to”, “operable to”, and “programmed to”do not imply any particular tangible or intangible modification of asubject, but, rather, are intended to be used interchangeably. Forexample, a processor configured to monitor and control an operation or acomponent may also mean the processor being programmed to monitor andcontrol the operation or the processor being operable to monitor andcontrol the operation. Likewise, a processor configured to execute codecan be construed as a processor programmed to execute code or operableto execute code.

A phrase such as an “aspect” does not imply that such aspect isessential to the subject technology or that such aspect applies to allconfigurations of the subject technology. A disclosure relating to anaspect may apply to all configurations, or one or more configurations. Aphrase such as an aspect may refer to one or more aspects and viceversa. A phrase such as a “configuration” does not imply that suchconfiguration is essential to the subject technology or that suchconfiguration applies to all configurations of the subject technology. Adisclosure relating to a configuration may apply to all configurations,or one or more configurations. A phrase such as a configuration mayrefer to one or more configurations and vice versa.

The word “example” is used herein to mean “serving as an example orillustration.” Any aspect or design described herein as “example” is notnecessarily to be construed as preferred or advantageous over otheraspects or designs.

All structural and functional equivalents to the elements of the variousaspects described throughout this disclosure that are known or latercome to be known to those of ordinary skill in the art are expresslyincorporated herein by reference and are intended to be encompassed bythe claims. Moreover, nothing disclosed herein is intended to bededicated to the public regardless of whether such disclosure isexplicitly recited in the claims. No claim element is to be construedunder the provisions of 35 U.S.C. §112, sixth paragraph, unless theelement is expressly recited using the phrase “means for” or, in thecase of a method claim, the element is recited using the phrase “stepfor.” Furthermore, to the extent that the term “include,” “have,” or thelike is used in the description or the claims, such term is intended tobe inclusive in a manner similar to the term “comprise” as “comprise” isinterpreted when employed as a transitional word in a claim.

What is claimed is:
 1. A power system, comprising: a first power switchoperable to connect a first circuit to a power supply; a second powerswitch operable to selectively connect a second circuit to the powersupply or another power supply; a storage capacitor; a first capacitorswitch operable to connect the storage capacitor to a charge source; asecond capacitor switch operable to connect the storage capacitor to thefirst circuit; a third capacitor switch operable to connect the storagecapacitor to the second circuit; and a power controller configured to:turn on the first capacitor switch to charge the storage capacitor fromthe charge source; turn off the first capacitor switch after the storagecapacitor is charged, when the first circuit is to be powered up, turnon the first power switch and the second capacitor switch to supplycurrent to the first circuit from the charge source and the storagecapacitor, and when the second circuit is to be powered up, turn on thesecond power switch and the third capacitor switch to supply current tothe second circuit from the respective power supply or the other powersupply and the storage capacitor.
 2. The power system of claim 1,wherein, the power controller is configured to turn off the first powerswitch when the first circuit is to be turned off or placed in a standbymode.
 3. The power system of claim 1, wherein, the power controller isconfigured to turn off the second power switch when the second circuitis to be turned off or placed in a standby mode.
 4. The power system ofclaim 1, wherein the first power switch has an adjustable resistance,and the power controller is configured to initially set the resistanceof the first power switch to a first resistance when the first circuitis to be powered up, and, after a time delay, to set the resistance ofthe first power switch to a second resistance, the second resistancebeing lower than the first resistance.
 5. The power system of claim 1,wherein the second power switch has an adjustable resistance, and thepower controller is configured to initially set the resistance of thesecond power switch to a third resistance when the second circuit is tobe powered up, and, after a time delay, to set the resistance of thesecond power switch to a fourth resistance, the fourth resistance beinglower than the third resistance.
 6. The power system of claim 1, whereinthe first circuit comprises a memory, and the second circuit compriseslogic.
 7. The power system of claim 6, wherein the first circuit is tobe powered up from a memory retention voltage to a voltage of the powersupply, the memory retention voltage being lower than the voltage of thepower supply.
 8. The power system of claim 1, wherein the charge sourcecomprises the power supply.
 9. A method for managing power provision toa circuit, the method comprising: providing: a first power switchoperable to connect a first circuit to a first power supply; a secondpower switch operable to selectively connect a second circuit to one ofthe first power supply or a second power supply; a storage capacitor; afirst capacitor switch operable to connect the storage capacitor to acharge source; a second capacitor switch operable to connect the storagecapacitor to the first circuit; a third capacitor switch operable toconnect the storage capacitor to the second circuit; and a powercontroller configured to: turn on the first capacitor switch to chargethe storage capacitor from the charge source; turn off the firstcapacitor switch after the storage capacitor is charged, when the firstcircuit is to be powered up, turn on the first power switch and thesecond capacitor switch to supply current to the first circuit from thecharge source and the storage capacitor, and when the second circuit isto be powered up, turn on the second power switch and the thirdcapacitor switch to supply current to the second circuit from therespective first power supply or the second power supply and the storagecapacitor.
 10. The method of claim 9, further comprising configuring thepower controller to turn off the first power switch when the firstcircuit is to be turned off or placed in a standby mode.
 11. The methodof claim 9, further comprising configuring the power controller to turnoff the second power switch when the second circuit is to be turned offor placed in a standby mode.
 12. The method of claim 9, wherein thefirst power switch has an adjustable resistance, and the method furthercomprises configuring the power controller to initially set theresistance of the first power switch to a first resistance when thefirst circuit is to be powered up, and, after a time delay, to set theresistance of the first power switch to a second resistance, the secondresistance being lower than the first resistance.
 13. The method ofclaim 9, wherein the second power switch has an adjustable resistance,and the method further comprises configuring the power controller toinitially set the resistance of the second power switch to a thirdresistance when the second circuit is to be powered up, and, after atime delay, to set the resistance of the second power switch to a fourthresistance, the fourth resistance being lower than the third resistance.14. The method of claim 9, wherein the first circuit comprises a memory,and the second circuit comprises logic.
 15. The method of claim 14,wherein the memory is to be powered up from a memory retention voltageto a voltage of the power supply, the memory retention voltage beinglower than the voltage of the power supply.
 16. The method of claim 9,wherein the charge source comprises the first or the second powersupply.
 17. An integrated circuit, comprising: memory connectable to afirst power supply via a first power switch; a logic circuit selectivelyconnectable to the first power supply or a second power supply via asecond power switch; a storage capacitor; a first capacitor switchoperable to connect the storage capacitor to a charge source; a secondcapacitor switch operable to connect the storage capacitor to thememory; a third capacitor switch operable to connect the storagecapacitor to the logic circuit; and a power controller configured to:turn on the first capacitor switch to charge the storage capacitor fromthe charge source; turn off the first capacitor switch after the storagecapacitor is charged, when the memory is to be powered up, turn on thefirst power switch and the second capacitor switch to supply current tothe memory from the charge source and the storage capacitor, and whenthe logic circuit is to be powered up, turn on the second power switchand the third capacitor switch to supply current to the logic circuitfrom the respective first power supply or the second power supply andthe storage capacitor.
 18. The integrated circuit of claim 17, wherein:the power controller is configured to turn off the first power switchwhen the memory is to be turned off or placed in a standby mode, and thepower controller is configured to turn off the second power switch whenthe logic circuit is to be turned off or placed in a standby mode. 19.The integrated circuit of claim 17, wherein the first power switch hasan adjustable resistance, and the power controller is configured toinitially set the resistance of the first power switch to a firstresistance when the memory is to be powered up, and, after a time delay,to set the resistance of the first power switch to a second resistance,the second resistance being lower than the first resistance.
 20. Thepower system of claim 17, wherein the second power switch has anadjustable resistance, and the power controller is configured toinitially set the resistance of the second power switch to a thirdresistance when the logic circuit is to be powered up, and, after a timedelay, to set the resistance of the second power switch to a fourthresistance, the fourth resistance being lower than the third resistance.